Figure 1 from Snapback Breakdown Dynamics and ESD Susceptibility of LDMOS | Semantic Scholar
GGNMOS ESD Protection Simulation
Characterization for ESD Design, the TLP Zoo: Part 1 | EOS/ESD Association, Inc.
High Voltage Tolerant ESD Protection Circuit for Plug and Play Devices
The Transistor: An Indispensable ESD Protection Device - Part 2 - In Compliance Magazine
Electronics | Free Full-Text | The ESD Characteristics of a pMOS-Triggered Bidirectional SCR in SOI BCD Technology
Snapback behavior determines ESD protection effectiveness - SemiWiki
An Off-Chip ESD Protection for High-Speed Interfaces - In Compliance Magazine
MODELING NMOS SNAPBACK CHARACTERISTIC USING PSPICE 1. Introduction 2. NMOS SNAPBACK
An improved GGNMOS triggered SCR for high holding voltage ESD protection applications
Technical considerations and protection mechanism for ESD event...
Esd | PDF
Electronics | Free Full-Text | The ESD Characteristics of a pMOS-Triggered Bidirectional SCR in SOI BCD Technology
Snapback breakdown ESD device based on zener diodes on silicon-on-insulator technology - ScienceDirect
Technical considerations and protection mechanism for ESD event...
High Trigger Current NPN Transistor With Excellent Double-Snapback Performance for High-Voltage Output ESD Protection | Semantic Scholar
Measured IV-curve and simplified model for ESD-protection elements with... | Download Scientific Diagram
Mix‐mode forward‐biased diode with low clamping voltage for robust ESD applications - Qi - 2020 - Electronics Letters - Wiley Online Library
Esd | PDF
A double snapback SCR ESD protection scheme for 28 nm CMOS process - ScienceDirect
A double snapback SCR ESD protection scheme for 28 nm CMOS process - ScienceDirect
PDF) Snapback circuit model for cascoded NMOS ESD over-voltage protection structures
Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations | Semantic Scholar
